1. Field of the Invention
The present invention generally relates to the packaging of integrated circuit chips and, more particularly, to package structures and materials for very large scale integrated circuits and packages including a plurality of such chips in which the reliability of connections is enhanced.
2. Description of the Prior Art
The advantages of very high integration density in regard to circuit performance and manufacturing economy have been recognized for some years. Connections of reduced length have reduced capacitance and resistance, reducing signal propagation time and power requirements while increasing noise immunity. Reduced signal propagation time and increased noise immunity can also be developed by minimizing the length of connections between chips, as well. Increased chip functionality can be obtained at lower manufacturing cost by forming more devices (e.g. transistors, storage cells and the like) on a single wafer. For these reasons, there is a trend toward producing larger chips and the packaging of many chips in the same package.
However, increased chip size also increases the dimensional change of the chip during thermal excursions. Moreover, including more chips within a single package as well as increased functionality of each chip tends to increase the amount of heat which must be dissipated by the package. This also increases the magnitude of temperature excursions and resultant dimensional changes of the chip and other structures in the package such as lead frames or laminated chip carriers for making mechanical and electrical connections to individual chips printed circuit boards for making connections between chips and to package terminals and connection structures between the chip carriers and the printed circuit board.
U.S. Pat. No. 5,956,235 to Kresge et al. and assigned to the assignee of the present application discloses a resilient connection for connecting surface metallization on a chip directly to surface metallization on a PCB. The resilient connection disclosed therein includes an upstanding structure including a core of resilient material such as a polymer coated with a conductive material such as metal. This structure apparently relies on a significant stand-off distance (apparently comparable to the transverse dimension of the connection) between the chip and the PCB in order to accommodate a large difference in in-plane CTE between the chip and PCB materials. (Henceforth CTE will refer to in-plane CTE and the units used shall Parts per million per degree C). This stand-off distance appears to compromise the mechanical connection between the PCB and the chip. Moreover, the high aspect ratio connections are substantially cantilevers which would be deflected during different relative accelerations of the chip and PCB, compromising reliability.
As is well known, silicon chips have a coefficient of thermal expansion (CTE) of 3.4 PPM/xc2x0C. while the CTE of conventional glass epoxy printed circuit boards (PCB) is much larger: about 17-20 PPM/xc2x0C. Alternative reinforced materials having intermediate CTEs which are more closely matched to the CTE of a chip are available such as S-glass, aramid, invar, LCP, etc. but are many times more expensive to purchase or process and prohibitive for most PCB production applications. However, such materials are more commonly and efficiently used for laminated chip carriers (LCC) which are of smaller size. An intermediate CTE material mechanically interposed between a chip and a glass epoxy PCB also serves to reduce stresses from thermal cycling imposed on the connections between the chip and the LCC and the LCC and the PCB. The connections between the chip and the LCC are preferably formed by well-known solder preforms while the connections between the LCC and the PCB are usually formed by a ball grid array; both of which are susceptible to damage such as cracking due to fatigue from repeated stressing by repeated temperature changes. Bonded wire connections are known to be more compliant but are time consuming and expensive to fabricate, present additional failure modes and are not capable of providing as many connections as bonding pads.
In general, it is considered preferable to provide a relatively close match between the CTE of the chip and the CTE of the LCC, particularly since the chips are relatively brittle and can crack under relatively low strain levels. Avoidance of damage to the chip is of high importance in this regard. It can be appreciated that the closeness of the match becomes more critical as chip size is increased. However, as the CTE of the LCC is more closely matched to the CTE of the chip, the difference in CTEs between the LCC and the PCB is increased with consequently increased stress on the ball grid array. As a partial solution, the use of a dielectric material exhibiting a low Youngs modulus of elasticity within at least one of the packaging levels is expected to reduce stress in the overall package. (Henceforth modulus shall refer to Youngs modulus and the units used shall be millions of pounds per square inch, MPSI). However, construction of advanced high density structures with some layers or packaging levels composed entirely of low modulus materials presents additional problems of dimensional stability as well as heat conduction and removal.
In summary, as chip sizes are increased, the CTEs of the chip and the LCC will need to be more closely matched, increasing the mismatch in CTEs between the LCC and other structures, greatly increasing the likelihood of failure of electrical and mechanical connections therebetween. Use of layers of low modulus materials present additional problems while not providing a complete solution to thermally induced mechanical stresses in the package. At the present state of the art, the use of materials having a CTE more closely matched to the chip is not economically feasible in most applications. At the present state of the art, the number and size of chips which can be included in a single package (and, hence, the level of both performance and functionality of an electronic package as well as its reliability) are limited by thermally induced stress at some or even many levels within the electronic circuit package.
It is therefore an object of the present invention to provide a package structure having low modulus materials only at points necessary for avoidance or reduction of thermally induced stress.
It is another object of the invention to provide an electronic circuit package structure having thermal conduction properties and dimensional stability which are not compromised by low modulus materials included in the package structure.
It is a further object of the invention to provide a mounting pad and electrical connection structure which is compliant in three orthogonal directions.
It is yet another object of the invention to provide increased number and size of chips which can be included in an electronic circuit package without compromising reliability.
It is yet another object of the invention to allow the CTE of a chip carrier to be closely matched to the CTE of a semiconductor chip without compromise of package reliability or requirement of particular PCB materials.
It is yet another object of the invention to provide electrical connections for electronic packages with increased tolerance for thermal mismatch.
In order to accomplish these and other objects of the invention, an electronic circuit package is provided including a plurality of packaging levels, a low aspect ratio deposit of low modulus material at a surface of a packaging structure included in the electronic circuit package, such as a PCB, and a layer of conductive material overlying the deposit of low modulus material and forming a compliant connection pad which is elastically deformable in three mutually orthogonal directions.
In accordance with another aspect of the invention, a compliant connection pad comprising a low aspect ratio deposit of low modulus material at a surface of a packaging structure, a layer of conductive material overlying the deposit of low modulus material and a connection from the packaging structure to the layer of conductive material.
In accordance with another aspect of the invention, a method of limiting stress applied to a chip in an electronic circuit package due to mismatch of packaging elements is provided comprising steps of attaching a chip to a chip carrier formed of a material having a coefficient of thermal expansion similar to that of the chip, and decoupling stress between the chip carrier and another packaging element with a compliant connection pad including a layer of low modulus material.
In accordance with a yet further aspect of the invention, a method of making a compliant connection pad is provided including steps of attaching a layer of low modulus material to a surface, laminating a metal layer to the low modulus material, patterning the metal layer to form a patterned metal layer, and removing unwanted low modulus material.